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1 ? fn6416.3 ISL84581 low-voltage, single and dual supply, 8-to-1 multiplexer the intersil ISL84581 device contains precision, bidirectional, analog switches configured as an 8-to-1 multiplexer/demultiplexer. it was designed to operate from a single +2v to +12v single su pply or from dual 2v to 6v supplies. the device has an inhibit pin to simultaneously open all signal paths. the ISL84581 has an on-resistance of 39 with a dual 5v supply and 125 with a single +3.3v supply. each switch can handle rail-to-rail analog signals. the off-leakage current is only 0.02na at +25c or 0.2na at +85c . all digital inputs have 0.8v to 2.4v logic thresholds, ensuring ttl/cmos logic compatibility wh en using a single 3.3v or +5v supply or dual 5v supplies. the ISL84581 is a single 8-to-1 multiplexer device. table 1 summarizes the performance of the part. related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? ? application note an557 ?recommended test procedures for analog switches? ? application note an520 ?cmos analog multiplexers and switches; specifications and application considerations.? ? application note an1034 ?analog switch and multiplexer applications? features ? fully specified at 3.3v, 5v, 5v, and 12v supplies for 10% tolerances ? on-resistance (r on ) max, v s = 4.5v . . . . . . . . . . . 50 ? on-resistance (r on ) max, v s = +3v. . . . . . . . . . . . 155 ?r on matching between channels, v s = 5v . . . . . . . . . <2 ? low charge injection, v s = 5v . . . . . . . . . . . . . 1pc (max) ? single supply operation. . . . . . . . . . . . . . . . . . . +2v to +12v ? dual supply operation . . . . . . . . . . . . . . . . . . . . . 2v to 6v ? fast switching action (v s = +5v) -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19ns ? guaranteed max off-leakage . . . . . . . . . . . . . . . . . . . 2.5na ? guaranteed break-before-make ? ttl, cmos compatible ? pb-free (rohs compliant) applications ? battery powered, handheld, and portable equipment ? communications systems -radios - telecom infrastructure - adsl, vdsl modems ? test equipment - medical ultrasound - magnetic resonance image - ct and pet scanners (mri) -ate - electrocardiograph ? audio and video signal routing ? various circuits - +3v/+5v dacs and adcs - sample and hold circuits - operational amplifier gain switching networks - high frequency analog switching - high speed multiplexing - integrator reset circuits table 1. features at a glance configuration single 8:1 mux 5v r on 39 5v t on /t off 32ns/18ns 12v r on 32 12v t on /t off 23ns/15ns 5v r on 65 5v t on /t off 38ns/19ns 3.3v r on 125 3.3v t on /t off 70ns/32ns package 16 ld tssop, 16 ld qsop data sheet april 13, 2009 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2007-2009. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6416.3 april 13, 2009 pinout ISL84581 (16 ld tssop, qsop) top view note: switches shown for logic ?0? inputs. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 no1 no3 com no7 no5 inh gnd v- v+ no4 no0 no6 addc addb adda no2 logic truth tables ISL84581 inh addc addb adda switch on 0000 no0 0001 no1 0010 no2 0011 no3 0100 no4 0101 no5 0110 no6 0111 no7 1xxx none note: logic ?0? 0.8v. logic ?1? 2.4v, with v+ between 2.7v and 10v. x = don?t care. pin descriptions pin function v+ positive power supply input v- negative power supply input. connect to gnd for single supply configurations. gnd ground connection inh digital control input. connect to gnd for normal operation. connect to v+ to turn all switches off. addx address input pin com analog switch common pin nox analog switch normally open pin ordering information part number (note) part marking temp range (c) package (pb-free) pkg. dwg. # ISL84581ivz 84581 ivz -40 to +85 16 ld tssop (4.4mm) m16.173 ISL84581ivz-t* 84581 ivz -40 to +85 16 ld tssop (4.4mm) tape and reel m16.173 ISL84581iaz 84581 iaz -40 to +85 16 ld qsop (4.4mm) m16.15a ISL84581iaz-t* 84581 iaz -40 to +85 16 ld qsop (4.4mm) tape and reel m16.15a * please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free plas tic packaged products employ special pb-free ma terial sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compat ible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. ISL84581
3 fn6416.3 april 13, 2009 absolute maximum rati ngs thermal information v+ to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 15v v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 15v v- to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15v to 0.3v input voltages inh, nox, addx (note 1). . . . . . . . . . . . . . . -0.3 to ((v+) + 0.3v) output voltages com (note 1) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((v+) + 0.3v) continuous current (any terminal) . . . . . . . . . . . . . . . . . . . . 30ma peak current nox, com (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . 100ma esd rating human body model (per mil-std-883, method 3015.7) . . >2.5kv thermal resistance (typical, note 2) ja (c/w) 16 ld tssop package . . . . . . . . . . . . . . . . . . . . . . 110 16 ld qsop package . . . . . . . . . . . . . . . . . . . . . . . 160 maximum junction temperature (plastic package). . . . . . . +150c maximum storage temperature range . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. signals on nox, com, addx, inh exceeding v+ or v- are clamped by internal diodes. li mit forward diode current to maximum curr ent ratings. 2. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications 5v supply test conditions: v supply = 4.5v to 5.5v, gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 3), unless otherwise specified. parameter test conditions temp (c) min (notes 4, 8) typ max (notes 4, 8) units analog switch characteristics analog signal range, v analog (note 10) full v- - v+ v on-resistance, r on v s = 4.5v, i com = 2ma, v no = 3v (see figure 5) 25 - 44 60 full - - 80 r on matching between channels, r on v s = 4.5v, i com = 2ma, v no = 3v (note 5) 25 - 1.3 4 full - - 6 r on flatness, r flat(on) v s = 4.5v, i com = 2ma, v no = 3v, 0.1v (note 6) 25 - 7.5 9 full - - 12 no off leakage current, i no(off) v s = 5.5v, v com = 4.5v, v no = + 4.5v (note 7) 25 - 0.02 - na full - 0.2 - na com off leakage current, i com(off) v s = 5.5v, v com = 4.5v, v no = + 4.5v (note 7) 25 - 0.02 - na full - 0.2 - na com on leakage current, i com(on) v s = 5.5v, v com = v no = 4.5v (note 7) 25 - 0.02 - na full - 0.2 - na digital input characteristics input voltage high, v inhh , v addh full 2.4 - - v input voltage low, v inhl , v addl full - - 0.8 v input current, i addh , i addl, i inhh , i inhl v s = 5.5v, v inh , v add = 0v or v+, (note 9) full -0.5 - 0.5 a dynamic characteristics inhibit turn-on time, t on v s = 4.5v, v no = 3v, r l = 300 , c l = 35pf, v in = 0 to 3 (see figure 1, note 9) 25 - 35 50 ns full - - 60 ns inhibit turn-off time, t off v s = 4.5v, v no = 3v, r l = 300 , c l = 35pf, v in = 0 to 3 (see figure 1, note 9) 25 - 22 35 ns full - - 40 ns address transition time, t trans v s = 4.5v, v no = 3v, r l = 300 , c l = 35pf, v in = 0 to 3 (see figure 1, note 9) 25 - 43 60 ns full - - 70 ns ISL84581
4 fn6416.3 april 13, 2009 break-before-make time, t bbm v s = 5.5v, v no = 3v, r l = 300 , c l = 35pf, v in = 0 to 3v (see figure 3, note 9) full 2 7 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 (see figure 2, note 9) 25 - 0.3 1 pc no off capacitance, c off f = 1mhz, v no = v com = 0v (see figure 6) 25 - 3 - pf com off capacitance, c off f = 1mhz, v no = v com = 0v (see figure 6) 25 - 21 - pf com on capacitance, c com(on) f = 1mhz, v no = v com = 0v (see figure 6) 25 - 26 - pf off-isolation r l = 50 , c l = 15pf, f = 100khz, v nox = 1v rms (see figures 4 and 18) 25 - 92 - db power supply characteristics power supply range (note 10) full 2 - 6 v positive supply current, i+ v s = 5.5v, v inh , v add = 0v or v+, switch on or off, (note 9) full -7 - 7 a negative supply current, i- full -1 - 1 a electrical specifications 5v supply test conditions: v supply = 4.5v to 5.5v, gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 3), unless otherwise specified. (continued) parameter test conditions temp (c) min (notes 4, 8) typ max (notes 4, 8) units electrical specific ations +12v supply test conditions: v+ = +10.8v to +13.2v, gnd = 0v, v inh = 4v, v inl = 0.8v (note 3), unless otherwise specified. parameter test conditions temp (c) min (notes 4, 8) typ max (notes 4, 8) units analog switch characteristics analog signal range, v analog (note 10) full 0 - v+ v on-resistance, r on v+ = 10.8v, i com = 1.0ma, v no = 9v (see figure 5) 25 - 37 45 full - - 55 r on matching between channels, r on v+ = 10.8v, i com = 1.0ma, v no = 9v (note 5) 25 - 1.2 2 full - - 2 r on flatness, r flat(on) v+ = 10.8v, i com = 1.0ma, v no = 3v, 6v, 9v (note 6) full - 5 - no off leakage current, i no(off) v+ = 13.2v, v com = 1v, 12v, v no = 12v, 1v (note 7) 25 - 0.02 - na full - 0.2 - na com off leakage current, i com(off) v+ = 13.2v, v com = 12v, 1v, v no = 1v, 12v (note 7) 25 - 0.02 - na full - 0.2 - na com on leakage current, i com(on) v+ = 13.2v, v com = 1v, 12v, v no = 1v, 12v, or floating (note 7) 25 - 0.02 - na full - 0.2 - na digital input characteristics input voltage high, v inhh , v addh full 3.7 3.3 - v input voltage low, v inhl , v addl full - 2.7 0.8 v input current, i addh , i addl, i inhh , i inhl v+ = 13.2v, v inh , v add = 0v or v+ full -0.5 - 0.5 a dynamic characteristics inhibit turn-on time, t on v+ = 10.8v, v no = 10v, r l = 300 , c l = 35pf, v in = 0 to 4 (see figure 1, note 9) 25 - 24 40 ns full - - 45 ns inhibit turn-off time, t off v+ = 10.8v, v no = 10v, r l = 300 , c l = 35pf, v in = 0 to 4 (see figure 1, note 9) 25 - 15 30 ns full - - 35 ns ISL84581
5 fn6416.3 april 13, 2009 address transition time, t trans v+ = 10.8v, v no = 10v, r l = 300 , c l = 35pf, v in = 0 to 4 (see figure 1, note 9) 25 - 27 50 ns full - - 55 ns break-before-make time delay, t d v+ = 13.2v, r l = 300 , c l = 35pf, v no = 10v, v in = 0 to 4 (see figure 3, note 9) full 2 5 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 (see figure 2, note 9) 25 - 2.7 5 pc off-isolation r l = 50 , c l = 15pf, f = 100khz (see figures 4 and 18) 25 - 92 - db no off capacitance, c off f = 1mhz, v no = v com = 0v (see figure 6) 25 - 3 - pf com off capacitance, c com(off) f = 1mhz, v no = v com = 0v (see figure 6) 25 - 21 - pf com on capacitance, c com(on) f = 1mhz, v no = v com = 0v (see figure 6) 25 - 26 - pf power supply characteristics power supply range (note 10) full 2 - 12 v positive supply current, i+ v+ = 13.2v, v inh , v add = 0v or v+, all channels on or off full -7 - 7 a electrical specific ations +12v supply test conditions: v+ = +10.8v to +13.2v, gnd = 0v, v inh = 4v, v inl = 0.8v (note 3), unless otherwise specified. (continued) parameter test conditions temp (c) min (notes 4, 8) typ max (notes 4, 8) units electrical specific ations 5v supply test conditions: v+ = +4.5v to +5.5v, v- = gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 3), unless otherwise specified. parameter test conditions temp (c) min (notes 4, 8) typ max (notes 4, 8) units analog switch characteristics analog signal range, v analog (note 10) full 0 - v+ v on-resistance, r on v+ = 4.5v, i com = 1.0ma, v no = 3.5v (see figure 5) 25 - 81 100 full - - 120 r on matching between channels, r on v+ = 4.5v, i com = 1.0ma, v no = 3v (note 5) 25 - 2.2 4 full - - 6 r on flatness, r flat(on) v+ = 4.5v, i com = 1.0ma, v no = 1v, 2v, 3v (note 6) full - 11.5 - no off leakage current, i no(off) v+ = 5.5v, v com = 1v, 4.5v, v no = 4.5v, 1v (note 7) 25 - 0.02 - na full - 0.2 - na com off leakage current, i com(off) v+ = 5.5v, v com = 1v, 4.5v, v no = 4.5v, 1v (note 7) 25 - 0.02 - na full - 0.2 - na com on leakage current, i com(on) v+ = 5.5v, v com = v no = 4.5v (note 7) 25 - 0.02 - na full - 0.2 - na digital input characteristics input voltage high, v inhh , v addh full 2.4 - - v input voltage low, v inhl , v addl full - - 0.8 v input current, i addh , i addl, i inhh , i inhl v+ = 5.5v, v inh , v add = 0v or v+, (note 9) full -0.5 - 0.5 a dynamic characteristics inhibit turn-on time, t on v+ = 4.5v, v no = 3v, r l = 300 , c l = 35pf, v in = 0 to 3v (see figure 1, note 9) 25 - 43 60 ns full - - 70 ns ISL84581
6 fn6416.3 april 13, 2009 inhibit turn-off time, t off v+ = 4.5v, v no = 3v, r l = 300 , c l = 35pf, v in = 0 to 3v (see figure 1, note 9) 25 - 20 35 ns full - - 40 ns address transition time, t trans v+ = 4.5v, v no = 3v, r l = 300 , c l = 35pf, v in = 0 to 3v (see figure 1, note 9) 25 - 51 70 ns full - - 85 ns break-before-make time, t bbm v+ = 5.5v, v no = 3v, r l = 300 , c l = 35pf, v in = 0 to 3v (see figure 3, note 9) full 2 9 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ( see figure 2, note 9) 25 - 0.6 1.5 pc off-isolation r l = 50 , c l = 15pf, f = 100khz, v nox = 1v rms (see figures 4 and 18) 25 - 92 - db power supply characteristics power supply range (note 10) full 2 - 12 v positive supply current, i+ v+ = 5.5v, v- = 0v, v inh , v add = 0v or v+, switch on or off, (note 9) full -7 - 7 a positive supply current, i- full -1 - 1 a electrical specific ations 5v supply test conditions: v+ = +4.5v to +5.5v, v- = gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 3), unless otherwise specified. (continued) parameter test conditions temp (c) min (notes 4, 8) typ max (notes 4, 8) units electrical specifications 3.3v supply test conditions: v+ = +3.0v to +3.6v, v- = gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 3), unless otherwise specified parameter test conditions temp (c) min (notes 4, 8) typ max (notes 4, 8) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 3.0v, i com = 1.0ma, v no = 1.5v (see figure 5) 25 - 135 180 full - - 200 r on matching between channels, r on v+ = 3.0v, i com = 1.0ma, v no = 1.5v (note 5) 25 - 3.4 8 full - - 10 r on flatness, r flat(on) v+ = 3.0v, i com = 1.0ma, v no = 0.5v, 1v, 2v (note 6) full - 34 - no off leakage current, i no(off) v+ = 3.6v, v com = 0v, 4.5v, v no = 3v, 1v (note 7) 25 - 0.02 - na full - 0.2 - na com off leakage current, i com(off) v+ = 3.6v, v com = 0v, 4.5v, v no = 3v, 1v (note 7) 25 - 0.02 - na full - 0.2 - na com on leakage current, i com(on) v+ = 3.6v, v com = v no = 3v (note 7) 25 - 0.02 - na full - 0.2 - na digital input characteristics input voltage high, v inhh , v addh full 2.4 - - v input voltage low, v inhl , v addl full - - 0.8 v input current, i addh , i addl, i inhh , i inhl v+ = 3.6v, v inh , v add = 0v or v+, (note 9) full -0.5 - 0.5 a dynamic characteristics inhibit turn-on time, t on v+ = 3.0v, v no = 1.5v, r l = 300 , c l = 35pf, v in = 0v to 3v (see figure 1, note 9) 25 - 82 100 ns full - - 120 ns ISL84581
7 fn6416.3 april 13, 2009 inhibit turn-off time, t off v+ = 3.0v, v no = 1.5v, r l = 300 , c l = 35pf, v in = 0v to 3v (see figure 1, note 9) 25 - 37 50 ns full - - 60 ns address transition time, t trans v+ = 3.0v, v no = 1.5v, r l = 300 , c l = 35pf, v in = 0v to 3v (see figure 1, note 9) 25 - 96 120 ns full - - 145 ns break-before-make time, t bbm v+ = 3.6v, v no = 1.5v, r l = 300 , c l = 35pf, v in = 0v to 3v (see figure 3, note 9) full 3 13 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ( see figure 2, note 9) 25 - 0.3 1 pc off-isolation r l = 50 , c l = 15pf, f = 100khz, v no = 1v rms (see figures 4 and 18) 25 - 92 - db power supply characteristics power supply range (note 10) full 2 - 12 v notes: 3. v in = input logic voltage to configure the device in a given state. 4. the algebraic convention, whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. 5. r on = r on (max) - r on (min). 6. flatness is defined as the difference between maximum and minimum value of on-resi stance over the specified analog signal ran ge. 7. leakage parameter is 100% tested at high temp, and guaranteed by correlation at +25c. 8. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. 9. limits established by characteri zation and are not production tested. 10. limits should be considered typi cal and are not production tested. electrical specifications 3.3v supply test conditions: v+ = +3.0v to +3.6v, v- = gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 3), unless otherwise specified (continued) parameter test conditions temp (c) min (notes 4, 8) typ max (notes 4, 8) units test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. inhibit t on /t off measurement points repeat test for other switches. c l includes fixture and stray capacitance. figure 1b. inhibit t on /t off test circuit 50% t r < 20ns t f < 20ns t on 3v 0v t off logic input switch output 90% 0v 90% v out vno0 v out v (no or nc) r l r l r on + ----------------------- - = logic input v out r l com no0 inh 300 35pf gnd v- c no1-no7 c l v+ adda-c c v+ c ISL84581
8 fn6416.3 april 13, 2009 logic input waveform is inverted for switches that have the opposite logic sense. figure 1c. address t trans measurement points repeat test for other switches. c l includes fixture and stray capacitance. figure 1d. address t trans test circuit figure 1. switching times figure 2a. q measurement points figure 2b. q test circuit figure 2. charge injection figure 3a. t bbm measurement points repeat test for other switches. c l includes fixture and stray capacitance. figure 3b. t bbm test circuit figure 3. break-before-make time test circuits and waveforms (continued) 50% t r < 20ns t f < 20ns t trans 90% 3v vno x 0v t trans logic input switch output 10% v out 0v vno0 v out v (no or nc) r l r l r on + ----------------------- - = logic input v out r l com no0 adda-c 300 35pf gnd no1-no6 c l v+ inh c v- c v+ c no7 v- c v out v out off on off q = v out x c l switch output logic input 3v 0v c l v out r g v g gnd com no logic input inh addx v- c v+ c repeat test for other switches. 1nf 0 80% 3v 0v t bbm logic input switch output 0v v out t r < 20ns t f < 20ns logic input adda-c com r l c l v out 35pf 300 no0-no7 gnd v+ c inh v- c v+ c ISL84581
9 fn6416.3 april 13, 2009 figure 4. off-isolation test circuit figure 5. r on test circuit figure 6. capacitance test circuit test circuits and waveforms (continued) analyzer r l signal generator 0v or v+ nox com addx gnd inh 0v or v+ v- c v+ c 0v or v+ no com addx gnd v nox v 1 r on = v 1 /1ma 1ma inh v- c v+ c gnd nox com addx impedance analyzer 0v or v+ inh v- c v+ c ISL84581
10 fn6416.3 april 13, 2009 detailed description the ISL84581 multiplexer offers precise switching capability from bipolar 2v to 6v supplies or a single 2v to 12v supply. when powered with dual 5v supplies the part has low on-resistance (39 ) and high speed operation (t on =38ns, t off = 19ns). it has an inhibit pin to simultaneously open all signal paths. the device is especially well suited for applications using 5v supplies. with 5v supplies the performance (r on , leakage, charge injection, etc.) is best in class. high frequency applications also benefit from the wide bandwidth and high off-isolation. supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the ic. all i/o pins contain esd protection diodes from the pin to v+ and to v- (see figure 7). to prevent forward biasing these diodes, v+ and v- must be applied before any input signals, and input signal voltages must remain between v+ and v-. if these conditions cannot be guaranteed, then one of the following two protection methods should be employed. logic inputs can easily be protected by adding a 1k resistor in series with the input (see figure 7). the resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. this method is not applicable for the signal path inputs. adding a series resistor to the switch input defeats the purpose of using a low r on switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see figure 7). these additional diodes limit the analog signal from 1v below v+ to 1v above v-. the low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. power-supply considerations the ISL84581 construction is ty pical of most cmos analog switches, in that it has three supply pins: v+, v-, and gnd. v+ and v- drive the internal cmos switches and set their analog voltage limits, so there are no connections between the analog signal path and gnd. unlike switches with a 13v maximum supply voltage, the ISL84581 15v maximum supply voltage provides plenty of room for the 10% tolerance of 12v supplies (6v or 12v single supply), as well as room for overshoot and noise spikes. the part performs equally well when operated with bipolar or single voltage supplies.the minimum recommended supply voltage is 2v single supply or 2v dual supply. it is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. refer to the ?electrical specification? tables on page 4 and ?typical performance curves? on page 11 for details. v+ and gnd power the internal logic setting the digital switching point of the level shifters. the level shifters convert the logic levels to switched v+ and v- signals to drive the analog switch gate terminals. logic-level thresholds v+ and gnd power the internal logic stages, so v- has no affect on logic thresholds. this ISL84581 is ttl compatible (0.8v and 2.4v) over a v+ supply range of 2.7v to 10v. at 12v the v ih level is about 3.3v. this is still below the cmos guaranteed high output minimum level of 4v, but noise margin is reduced. for best results with a 12v supply, use a logic family that provides a v oh greater than 4v. the digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. driving the digital input signals from gnd to v+ with a fast transition time minimizes power dissipation. high-frequency performance in 50 systems, signal response is reasonably flat even past 100mhz (see figures 16 and 17). figures 16 and 17 also illustrate that the frequency res ponse is very consistent over varying analog signal levels. an off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch?s input to its output. off-isolation is the resistance to this feed through. figure 18 details the high off isolation of the ISL84581. at 10mhz, off-isolation is about 55db in 50 systems, decreasing app roximately 20db per decade as frequency increases. higher load impedances decrease off-isolation due to the voltage divider action of the switch off impedance and the load impedance. figure 7. input overvoltage protection v com v nox optional protection v+ logic diode optional protection diode optional protection resistor for logic inputs 1k v- ISL84581
11 fn6416.3 april 13, 2009 leakage considerations reverse esd protection diodes are internally connected between each analog-signal pin and both v+ and v-. one of these diodes conducts if any analog signal exceeds v+ or v-. virtually all the analog leakage current comes from the esd diodes to v+ or v-. although the esd diodes on a given signal pin are identical and t herefore fairly well balanced, they are reverse biased differently. each is biased by either v+ or v- and the analog signal. this means their leakages will vary as the signal varies. the difference in the two diode leakages to the v+ and v- pins constitutes the analog-signal-path leakage current. all analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. this is why both sides of a given sw itch can show leakage currents of the same or opposite polarity. there is no connection between the analog signal paths and gnd. typical performance curves t a = +25c, unless otherwise specified figure 8. on-resistance vs supply voltage figure 9. on-resistance vs switch voltage figure 10. on-resistance vs switch voltage figure 11. on-resistance vs switch voltage 30 40 50 60 70 100 200 300 400 -40c +85c v- = 0v r on ( ) v+ (v) 4681012 357911 2 0 20 v com = (v+) - 1v i com = 1ma v- = -5v +25c -40c +85c +25c 20 30 40 50 60 30 40 50 60 70 80 90 50 60 70 80 90 100 110 120 r on ( ) v com (v) -4 -2 0 2 4 -5 -3 -1 1 3 5 v s = 5v i com = 1ma v s = 2v +25c +85c +25c -40c +85c -40c +25c -40c +85c v s = 3v 75 100 150 200 225 60 80 100 120 140 160 40 50 60 70 80 90 100 r on ( ) v com (v) 024 135 v+ = 2.7v v+ = 5v +25c -40c +85c i com = 1ma v- = 0v +25c -40c +85c v- = 0v +25c +85c -40c v- = 0v v+ = 3.3v 175 125 r on ( ) v com (v) 024681012 20 25 30 35 40 45 50 55 60 i com = 1ma -40c +85c +25c v+ = 12v v- = 0v ISL84581
12 fn6416.3 april 13, 2009 figure 12. inhibit turn-on time vs supply voltage fig ure 13. inhibit turn-off time vs supply voltage figure 14. address trans time vs single supply voltage figure 15. address trans time vs dual supply voltage figure 16. frequency response figure 17. frequency response typical performance curves t a = +25c, unless otherwise specified (continued) 0 100 200 300 400 500 0 50 100 150 200 250 t on (ns) v+ (v) 24681012 357911 -40c +85c v- = 0v v- = -5v v com = (v+) - 1v -40c +85c -40c +25c +25c +25c +25c 0 50 100 150 200 0 20 40 60 80 100 t off (ns) v+ (v) 2 4 6 8 10 12 357911 -40c 85c v com = (v+) - 1v v- = 0v v- = -5v -40c 85c -40c 25c 25c +25c 0 50 100 150 200 0 20 40 60 80 100 t off (ns) v+ (v) 2 4 6 8 10 12 357911 -40c +85c v com = (v+) - 1v v- = 0v v- = -5v -40c +85c -40c +25c +25c +25c 24681012 35791113 v+ (v) +85c v- = 0v v com = (v+) - 1v -40c 0 50 100 150 200 250 300 t rans (ns) +25c v (v) 23456 v com = (v+) - 1v t rans (ns) 50 100 150 200 250 +85c -40c +25c 0 frequency (hz) 3 0 -3 normalized gain (db) 0 45 90 135 180 phase () 1m 10m 100m 600m v in = 0.2v p-p to 5v p-p gain phase v s = 5v r l = 50 frequency (hz) 3 0 -3 normalized gain (db) 0 45 90 135 180 phase () 1m 10m 100m 600m v in = 0.2v p-p to 4v p-p gain phase v s = 3v r l = 50 ISL84581
13 fn6416.3 april 13, 2009 die characteristics substrate potential (powered up): v- transistor count: 193 process: si gate cmos figure 18. off isolation figure 19. charge injection vs switch voltage typical performance curves t a = +25c, unless otherwise specified (continued) frequency (hz) 1k 100k 1m 100m 500m 10k 10m -110 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 off isolation (db) isolation r l = 50 v s = 2v to 5v v+ = 3v to 12v or q (pc) v com (v) -5 0 5 10 12 -4 -3 -2 -1 0 1 2 3 -2.5 2.5 7.5 v s = 5v v+ = 5v v- = 0v v+ = 12v v- = 0v v+ = 3.3v v- = 0v ISL84581
14 fn6416.3 april 13, 2009 ISL84581 shrink small outline plastic packages (ssop) quarter size outline plastic packages (qsop) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum material condition. 10. controlling dimension: inches. converted millimeter dimen- sions are not necessarily exact. index area e d n 123 -b- 0.17(0.007) c a m b s e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 m16.15a 16 lead shrink small outline plastic package (0.150? wide body) symbol inches millimeters notes min max min max a 0.061 0.068 1.55 1.73 - a1 0.004 0.0098 0.102 0.249 - a2 0.055 0.061 1.40 1.55 - b 0.008 0.012 0.20 0.31 9 c 0.0075 0.0098 0.191 0.249 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.81 3.99 4 e 0.025 bsc 0.635 bsc - h 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 l 0.016 0.035 0.41 0.89 6 n16 167 0 8 0 8 - rev. 2 6/04
15 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6416.3 april 13, 2009 ISL84581 thin shrink small outlin e plastic packages (tssop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ab, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. (angles in degrees) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 0.05(0.002) m16.173 16 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.043 - 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.033 0.037 0.85 0.95 - b 0.0075 0.012 0.19 0.30 9 c 0.0035 0.008 0.09 0.20 - d 0.193 0.201 4.90 5.10 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.020 0.028 0.50 0.70 6 n16 167 0 o 8 o 0 o 8 o - rev. 1 2/02

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